1. Field of the Invention The present invention relates to a memory system including a nonvolatile semiconductor storage device, and, more particularly to a technique for improving a Wear-leveling control system in a memory system having a data area in which data is frequently rewritten and a data area hardly written mixed therein.
2. Description of the Related Art
As one of semiconductor storage devices, a flash memory. that can be electrically written is known. Above all, a NAND flash memory in which plural memory cells are connected in series to constitute a NAND cell block attracts attention as a flash memory that can be highly integrated.
One memory cell of the NAND flash memory has a FETMOS structure in which a floating gate (a charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. The plural memory cells are connected and constitute NAND cells in series such that sources and drains are shared among the memory cells adjacent to one another. Such NAND cells are arrayed in matrix to constitute a memory cell array.
The drains at one end side of the NAND cells arranged in a column direction of the memory cell array are commonly connected to a bit line via selection gate transistors, respectively. The sources on the other end side are also commonly connected to a source line via selection gate transistors. Word lines of memory cell transistors and gate electrodes of the selection gate transistors are commonly connected in a row direction of the memory cell array as a word line (a control gate line) and a selection gate line, respectively.
Such a NAND flash memory is disclosed in, for example, K.-D. Suh et al., “A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, November 1995 and Y. Iwata et al., “A 35ns Cycle Time 3.3V Only 32 Mb NAND Flash EEPROM,” IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, November 1995.
FIG. 1 is a diagram showing a block and page arrangement of a binary 2-Gbit NAND flash memory.
As shown in FIG. 1, a 2-Gbit chip includes 2048 blocks BLK of 128 KB and is constituted by 2 Gb=256 MB=128 KB×2048. Each of blocks BLK0 to BLK2047 includes 64 pages of 2 KB and is constituted by 128 KB=2 KB×64.
As a system including the NAND flash memory described above, for example, systems disclosed in E. Harari et al.,“Flash EEPROM System,” U.S. Pat. No. 5,602,987, Feb. 11, 1997, P. Estakhri et al., “Moving Sectors Within A Block OF Information In A Flash Memory Mass Storage Architecture,” U.S. Pat. No. 5, 907,856, May 25, 1999, and D. Moran et al., “Flash Memory System Providing Both Bios and User Storage Capability,” U.S. Pat. No. 5,519,843, May 21, 1996 are known.
In a memory system including a flash memory, Wear-leveling control is performed to prevent rewriting from being concentrated in a specific physical address block.
In the flash memory, in rewriting stored data, the stored data has to be erased before writing. An old block that has already become unnecessary is erased in advance, new data is written in the block erased, and a logical block address of the block is updated.
On the other hand, it is said that a life in terms of the number of times of rewriting of the NAND flash memory is 0.3 to 1×106 times for a binary product that stores 1-bit data in one memory cell.
Therefore, it is an object of the Wear-leveling control to perform control to prevent rewriting from being concentrated in a block of a specific physical address.
There are roughly two kinds of systems in the Wear-leveling control: Passive-wear-leveling and Active-wear-leveling.
In the Passive-wear-leveling, a block of a physical address not to be rewritten is left as it is and, in rewriting only a block of a physical address to be rewritten, the block is replaced with a block of an arbitrary physical address erased such that the Wear-leveling control can be automatically performed. In the Active-wear-leveling, rewriting is performed in blocks of all physical addresses including a block of a physical address not to be rewritten such that numbers of times of rewriting are averaged.
The Active-wear-leveling is disclosed in, for example, K. M. J. Lofgren et al., “Wear Leveling Techniques for Flash EEPROM Systems,” U.S. Pat. No. 6,594,183 B1, Jul. 15, 2003.